Overview Of Interrupt Handling

An interrupt handler, also known as an interrupt service routine (ISR), is a callback subroutine in an operating system or device driver whose execution is triggered by the reception of an interrupt. Interrupt handlers have a multitude of functions, which vary based on the reason the interrupt was generated and the speed at which the Interrupt Handler completes its task.

An interrupt handler is a low-level counterpart of event handlers. These handlers are initiated by either hardware interrupts or interrupt instructions in software, and are used for servicing hardware devices and transitions between protected modes of operation such as system calls.
When an interrupt is processed, a specific sequence of events takes place. You should write the interrupt service request (ISR) and interrupt service thread (IST) for your device driver with the following sequence of events in mind :

- When an interrupt occurs, the microprocessor jumps to the kernel exception handler.
- The exception handler disables all interrupts of an equal and lower priority at the microprocessor, and then calls the appropriate ISR for the physical interrupt request (IRQ).
- The ISR returns a logical interrupt, in the form of an interrupt identifier, to the interrupt handler and typically masks the board-level device interrupt.
- The interrupt handler re-enables all interrupts at the microprocessor, with the exception of the current interrupt, which is left masked at the board, and then signals the appropriate IST event.
- The IST is scheduled, services the hardware, and then finishes processing the interrupt.
- The IST calls the InterruptDone function, which in turn calls the OEMInterruptDone function in the OAL.

OEMInterruptDone re-enables the current interrupt.

Edge Triggered Interrupts

An edge-triggered interrupt is a class of interrupts that are signalled by a level transition on the interrupt line, either a falling edge (1 to 0) or a rising edge (0 to 1). A device wishing to signal an interrupt drives a pulse onto the line and then releases the line to its quiescent state. If the pulse is too short to be detected by polled I/O then special hardware may be required to detect the edge. This type of interrupt is useful for a fleeting signal that doesn't last long enough for the processor to recognize it using polled I/O or for when the signal can last a long time, but the significant event is when that signal first goes active.
Edge-triggered interrupt modules can be acknowledged immediately, no matter how the interrupt source behaves. The type of the interrupt source does not matter. It can be a pulse, a firmware-clear signal, or some external signal that eventually is cleared somehow. Edge-triggered interrupts keep firmware’s code complexity down, reduce the number of conditions firmware needs to be aware of, and provide more flexibility when interrupts are acknowledged. This keeps development time down and quality up.
Multiple devices may share an edge-triggered interrupt line if they are designed to. The interrupt line must have a pull-down or pull-up resistor so that when not actively driven it settles to one particular state.Devices signal an interrupt by briefly driving the line to its non-default state, and let the line float (do not actively drive it) when not signaling an interrupt. This type of connection is also referred to as open collector. The line then carries all the pulses generated by all the devices.
Edge-triggered interrupts do not suffer the problems that level-triggered interrupts have with sharing. Service of a low-priority device can be postponed arbitrarily, and interrupts will continue to be received from the high-priority devices that are being serviced. If there is a device that the CPU does not know how to service, it may cause a spurious interrupt, or even periodic spurious interrupts, but it does not interfere with the interrupt signaling of the other devices.

Level Triggered Interrupts

Level-triggered Interrupt : It is the class of interrupts where the presence of an unserviced interrupt is indicated by a high level (1), or low level (0), of the interrupt request line. A device wishing to signal an interrupt drives the line to its active level, and then holds it at that level until serviced. It ceases asserting the line when the CPU commands it to or otherwise handles the condition that caused it to signal the interrupt.

Level-triggered interrupts force firmware engineers to take into account what is generating the interrupt source. If the interrupt source is just a pulse from a state machine, then the device drivers do not need to do any additional work. If the interrupt source is asserted when a counter equals zero, the device driver must first write a non-zero value to the counter before it can acknowledge the interrupt. If the interrupt source is a signal from a different block with its own device driver or an external device under its own firmware control the device driver has no control over when the interrupt source is cleared. Its only choice is to disable that interrupt so that it can exit the interrupt handler.

There are also serious problems with sharing level-triggered interrupts. As long as any device on the line has an outstanding request for service the line remains asserted, so it is not possible to detect a change in the status of any other device. Deferring servicing a low-priority device is not an option, because this would prevent detection of service requests from higher-priority devices. If there is a device on the line that the CPU does not know how to service, then any interrupt from that device permanently blocks all interrupts from the other devices.

Overview of Interrupts

An interrupt is an unexpected hardware initiated subroutine call or jump that temporarily suspends the running of the current program.
Interrupts occur when a peripheral device asserts an interrupt input pin of the micro-processor. Provided the interrupt is permitted, it will be acknowledged by the processor at the end of the current memory cycle. The processor then services the interrupt by branching to a special service routine written to handle that particular interrupt. Upon servicing the device, the processor is then instructed to continue with what is was doing previously by use of the "return from interrupt" instruction.
Interrupts in general can be divided into two kinds- maskable and non-maskable.
A maskable interrupt is an interrupt whose trigger event is not always important, so the programmer can decide that the event should not cause the program to jump. A non-maskable interrupt (like the reset button) is so important that it should never be ignored. The processor will always jump to this interrupt when it happens.

The function that is called or the particular assembly code that is executed when the interrupt happens is called the Interrupt Service Routine (ISR). Other terms of note are: An interrupt flag (IFG) this is the bit that is set that triggers the interrupt, leaving the interrupt resets this flag to the normal state. An interrupt enable (IE) is the control bit that tells the processor that a particular maskable interrupt should or should not be ignored.

Advantages of Interrupts :
Interrupts are used to ensure adequate service response times by the processing. Sometimes, with software polling routines, service times by the processor cannot be guaranteed, and data may be lost. The use of interrupts guarantees that the processor will service the request within a specified time period, reducing the likelihood of lost data.

Software Interrupt :
The Software Interrupt (SWI) is an instruction that can be placed anywhere within a program. It forces the microprocessor to act as if an interrupt has occurs. The vector for the 6800 is located at addresses $FFFA and $FFFB. The SWI is often used by Monitor Programs to set breakpoints, which stops the program at a particular location so that the contents of the memory and registers can be examined.

Interrupt Latency :
The time interval from when the interrupt is first asserted to the time the CPU recognizes it. This will depend much upon whether interrupts are disabled, prioritized and what the processor is currently executing.

Interrupt Response Time :
The time interval between the CPU recognizing the interrupt to the time when the first instruction of the interrupt service routine is executed. This is determined by the processor architecture and clock speed.

Concept of Buffers

In computing, a buffer is a region of memory used to temporarily hold data while it is being moved from one place to another. Typically, the data is stored in a buffer as it is retrieved from an input device (such as a keyboard) or just before it is sent to an output device (such as a printer). However, a buffer may be used when moving data between processes within a computer.
Buffering is used to improve several other areas of computer performance as well. Most hard disks use a buffer to enable more efficient access to the data on the disk. Video cards send images to a buffer before they are displayed on the screen (known as a screen buffer). Computer programs use buffers to store data while they are running. If it were not for buffers, computers would run a lot less efficiently and we would be waiting around a lot more.
Buffers are another way that receivers can ensure that they do not miss any data sent to them. Buffers can also be useful on the transmit side, where they can enable applications to work more efficiently by storing data to be sent as the link is available.
The buffers may be in hardware, software, or both. When the hardware buffers aren't large enough, a PC may also use software buffers, which are programmable in size and may be as large as system memory permits. The port's software driver transfers data between the software and hardware buffers.
In micro controllers, the buffers tend to be much smaller, and some chips have no hardware buffers at all. The smaller the buffers, the more important it is to use other techniques to ensure that no data is missed.

Handshaking Mechanism

Handshaking is an automated process of negotiation that dynamically sets parameters of a communications channel established between two entities before normal communication over the channel begins. It follows the physical establishment of the channel and precedes normal information transfer.
It is usually a process that takes place when a computer is about to communicate with a foreign device to establish rules for communication. When a computer communicates with another device like a modem, printer, or network server, it needs to handshake with it to establish a connection.
With handshaking signals, a transmitter can indicate when it has data to send, and a receiver can indicate when it is ready to receive data. The exact protocols that signals follow may vary, though many RS-232 and RS-485 links follow standard or conventional protocols.

In hardware handshaking, the receiver brings a line high when it is ready to receive data, and the transmitter waits for this signal before sending data. The receiver may bring the line low any time and the transmitter must detect this, stop sending, and wait for the line to return high before finishing the transmission.
Other links accomplish the same thing with software handshaking, by having the receiver send one code to indicate that it is ready to receive, and another to signal the transmitter to stop sending.

Data Formats

The data bits in a serial transmission may represent anything, including commands, sensor readings, status information, error codes, or text messages. The information may be encoded as binary or text data.

- Binary Data : The receiver interprets a received byte as a binary number with a value from 0 to 255. The bits are numbered 0 through 7, with each bit representing the bit's value (0 or 1) multiplied by a power of 2. A byte of 1111 1111 translates to 255 or FFh and 0001 0001 translates to 17 or 11h. In asynchronous mode, bit 0, the least-significant bit arrives first. Binary data works fine for many links but some links need to send messages or files containing text.

- Text Data : To send text, the program uses a code that assigns a numeric value to each text character. There are several coding conventions :
* ASCII : It consists of 128 codes and requires only seven data bits. An eighth bit, if used, may be 0 or a parity bit.
* ANSI : It consists of 256 codes with the higher codes representing special and accented characters.
Other formats use 16 bits per character, which allows 65,536 different characters.

One can also use text to transfer binary data by expressing the data in ASCII Hex format. Each byte is represented by a pair of ASCII codes that represent the byte's two hexadecimal characters. This format can represent any value using only the ASCII codes 30h through 39h (from 0 through 9) and 41h to 46h (for A through F).