What is DRAM? In which form does it store data?

The random access memory is of two types out of which one is dynamic random access memory or DRAM and the other one is SRAM or static random access memory. 

Here we shall focus up on the first type i.e., the Dynamic RAM. 

What is Dynamic Random Access Memory (DRAM)?

- In dynamic RAM, each bit of the data is stored in a separate capacitor. 

- All these capacitors are housed within an IC (integrated circuit).

- These capacitors can be in either of the two states:

1. Charged and
2. Discharged

- The two values of a bit are represented by means of these two states only. 

- The two values of bit are 0 and 1. 

- However, there is a disadvantage of the dynamic RAM. 

- These capacitors tend to leak charge and therefore may lose all the stored information. 

- Therefore, it is very important to keep the capacitors flushing with fresh charge. 

- They are refreshed at regular intervals of time. 

- It is because of this refreshing requirement this type of RAM has been named so. 

- The main memory or the physical memory of the CPU is constituted of this dynamic RAM only.

- Apart from desktops, DRAM is also used in workstation systems, laptops, video game consoles etc. 

- The structural simplicity is one of the biggest advantages of the DRAM. 

- For each bit it only requires one capacitor and one transistor, whereas SRAM requires 4 to 6 transistors for the same purpose. 

- This enables the dynamic RAM to attain very high density. 

- DRAM is a volatile memory unlike the flash memory and so it loses data whenever the power supply is cut.

- The capacitors and the transistors it uses are extremely small and so billions of them can be easily be integrated in to one single memory chip.

- DRAM consists of array of charge storage cells arranged in a sort of rectangular way. 

- Each of the cells consists of one transistor and one capacitor. 

- Word lines are the horizontal lines that connect the rows with each other. 

- Two bit lines compose each of the columns of cells. 

- These lines are called the + and – bit lines.

- It is specified by the manufacturers that at what rate the storage cell capacitors are to be refreshed. 

- Typically, it is less than or equal to 64 ms. 

- The DRAM controller consists of the refresh logic that is responsible for automating the periodic refresh. 

- This job cannot be done by any other software and hardware. 

- Thus, the circuit of the controller is very complicated. 

- The capacity of DRAM per unit surface is greater than that of the SRAM. 

- Some systems may refresh one row at one instant while others may refresh all the rows simultaneously every 64 ms.  

- Some systems use an external timer based up on whose timing they refresh a part of the memory. 

- Many of the DRAM chips come with a counter that keeps track of which row is to be refreshed next.

- However, there are some conditions under which the data can be recovered even if the DRAM has not been refreshed since few minutes. 

- Bits of the DRAM might flip to opposite state spontaneously because of the electromagnetic interference in the system. 

- Background radiation is the major cause for the occurrence of the majority of the soft errors.

- Because of these errors the contents of the memory cells may change and circuitry might be harmed. 

- Redundant memory bits along with the memory controllers are one potential solution to this problem. 

- These bits are within the modules of the RAM. 

- The parity is recorded by these bits which enable the reconstruction of the missing data via ECC or error – correcting code.